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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * accompanied this code).
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package org.graalvm.compiler.lir.amd64;

import static jdk.vm.ci.code.ValueUtil.asRegister;
import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG;

import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler;
import org.graalvm.compiler.lir.LIRInstructionClass;
import org.graalvm.compiler.lir.Opcode;
import org.graalvm.compiler.lir.asm.CompilationResultBuilder;

import jdk.vm.ci.meta.AllocatableValue;

/**
 * AMD64 rdpid operation. The processor ID is put in the destination register. Note that the
 * processor ID is the contents of IA32_TSC_AUX, so it's up to the OS to set it. Linux apparently
 * puts 12-bits for the chip ID, followed by 12-bits for the CPU ID.
 */
@Opcode("RDPID")
public class AMD64ReadProcid extends AMD64LIRInstruction {
    public static final LIRInstructionClass<AMD64ReadProcid> TYPE = LIRInstructionClass.create(AMD64ReadProcid.class);

    @Def({REG}) protected AllocatableValue procidResult;

    public AMD64ReadProcid(AllocatableValue dst) {
        super(TYPE);

        this.procidResult = dst;
    }

    @Override
    public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
        masm.rdpid(asRegister(procidResult));
    }
}
